? motorola inc., 1994 motorola product information semiconductor order this document by DSP56002p/d DSP56002 dsp56l002 product brief 24-bit digital signal processor the DSP56002 and the dsp56l002 are mpu-style general purpose digital signal processors (dsps), composed of an ef?ient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. the 56000-family-compatible dsp core is fed by on- chip program ram, two independent data rams, and two data roms with sine and a-law and m -law tables. the DSP56002/l002 contains a serial communication interface (sci), synchronous serial interface (ssi), parallel host interface (hi), timer/event counter, phase-locked loop (pll), and on-chip emulation (once ) port. this combination of features, illustrated in figure 1, makes the DSP56002/l002 a cost-effective, high-performance solution for high-precision general- purpose digital signal processing. figure 1 DSP56002/l002 block diagram address 16 y data memory 256 24 ram 256 24 rom x data memory 256 24 ram 256 24 rom program memory 512 24 ram 64 24 rom program control unit 24-bit 56000 dsp core once tm port pll clock gen. 1 24-bit timer / event counter 6 sync. serial (ssi) or i/o 3 serial comm. (sci) or i/o 15 host interface (hi) or i/o 16-bit bus 24-bit bus external address bus switch data 24 external data bus switch control 10 bus control data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators gdb pdb xdb ydb pa b xab ya b interrupt control program decode controller program address generator 3 irq 4 7 internal data bus switch address generation unit (boot) (a-law / m -law) (sine) motorola reserves the right to change or discontinue this product without notice. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola DSP56002/l002 product information 1 DSP56002/l002 features digital signal processing core efficient, object code compatible, 24-bit 56000-family dsp engine up to 33 million instructions per second (mips) ?30.3 ns instruction cycle at 66 mhz up to 198 million operations per second (mops) at 66 mhz performs a 1024-point complex fast fourier transform (fft) in 59,898 clocks highly parallel instruction set with unique dsp addressing modes two 56-bit accumulators including extension byte parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle fractional and integer arithmetic with support for multiprecision arithmetic hardware support for block-floating point fft hardware nested do loops zero-overhead fast interrupts (2 instruction cycles) four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip memory on-chip harvard architecture permitting simultaneous accesses to program and two data memories 512 24-bit on-chip program ram and 64 24-bit bootstrap rom two 256 24-bit on-chip data rams two 256 24-bit on-chip data roms containing sine, a-law and m -law tables external memory expansion with 16-bit address and 24-bit data buses bootstrap loading from external data bus, host interface, or serial communications interface peripheral and support circuits byte-wide host interface (hi) with direct memory access support synchronous serial interface (ssi) to communicate with codecs and synchronous serial devices up to 32 software-selectable time slots in network mode serial communication interface (sci) for full-duplex asynchronous communications 24-bit timer/event counter also generates and measures digital waveforms on-chip peripheral registers memory mapped in data memory space double buffered peripherals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 DSP56002/l002 product information motorola up to 25 general purpose i/o (gpio) pins three external interrupt request pins; one non-maskable on-chip emulation (once) port for unobtrusive, processor speed-independent debugging software-programmable, phase-locked loop-based (pll) frequency synthesizer for the core clock power-saving wait and stop modes fully static, hcmos design for operating frequencies from 66 mhz or 40 mhz down to dc 132-pin ceramic pin grid array (pga) package; 13 13 array 132-pin plastic quad flat pack (pqfp) surface-mount package; 24 24 4 mm 144-pin thin quad flat pack (tqfp) surface-mount package; 20 20 1.4 mm 3.3 v (dsp56l002) and 5 v (DSP56002) power supply options the DSP56002 and dsp56l002 are identical except that the DSP56002 operates at 5 volts, while the dsp56l002 operates at 3.3 volts with a resultant reduction in power consumption and the need for fewer batteries in a portable application. documentation the three documents listed in table 1 are required for a complete description of the DSP56002/l002 and are necessary to properly design with the part. documentation is avail- able from a local motorola distributor, a motorola semiconductor sales of?e, or a motorola literature distribution center listed on the back page. table 1 DSP56002/l002 documentation topic description order number dsp56000 family manual detailed description of the 56000- family architecture and the 16-bit core processor and instruction set dsp56kfamum/ad DSP56002 user s manual detailed description of memory, peripherals, and interfaces DSP56002um/ad DSP56002/l002 data sheet electrical and timing speci?ations, and pin and package descriptions DSP56002/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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